SH7052 datasheet(828/919 Pages) RENESAS

828 / 919 page

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23.5

Sleep Mode

23.5.1

Transition to Sleep Mode

Executing the SLEEP instruction after the software standby bit (SSBY) in SBYCR has been

cleared to 0 causes a transition from the program execution state to sleep mode. Although the CPU

halts immediately after executing the SLEEP instruction, the contents of its internal registers

remain unchanged. The on-chip peripheral modules continue to run during sleep mode.

23.5.2

Canceling Sleep Mode

Cancellation by Interrupt: When an interrupt occurs, sleep mode is canceled and interrupt

exception processing is executed. The sleep mode is not canceled if the interrupt cannot be

accepted because its priority level is equal to or less than the mask level set in the CPU’s status

module.

Cancellation by DMA Address Error: If a DMA address error occurs, sleep mode is canceled

and DMA address error exception processing is executed.

Cancellation by Manual Reset: When an internal manual reset is triggered by the WDT and the

CPU acquires the bus during the internal manual reset period, the state of the

SH7052F/SH7053F/SH7054F changes to the manual reset state and sleep mode will be released.

Cancellation by Power-On Reset: A power-on reset of the SH7052F/SH7053F/SH7054F

resulting from driving the

RES pin low, or caused by the WDT, cancels sleep mode.

SH7052 Datasheet(PDF) 828 Page - Renesas Technology Corp