SH7052 datasheet(825/919 Pages) RENESAS

825 / 919 page

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Table 23.4

On-Chip Peripheral Module

Registers Initialized

Registers that Retain Data

Interrupt controller (INTC)

—

All registers

User break controller (UBC)

—

All registers

Bus state controller (BSC)

—

All registers

Direct memory access

controller (DMAC)

All registers

—

Advanced timer unit (ATU)

All registers

—

Advanced pulse controller

(APC)

—

All registers

Watchdog timer

(WDT)

• Bits 7 to 5 (OVF, WT/IT,

TME) of the timer control

status register (TCSR)

• Reset control/status register

(RSTCSR)

• Timer counter (TCNT)

• Bits 2 to 0 (CKS2 to CKS0)

of TCSR

Compare match timer (CMT)

All registers

—

HCAN

Registers other than

MC0[1:8] to MC15[1:8]

MD0[1:8] to MD15[1:8]

MC0[1:8] to MC15[1:8]

MD0[1:8] to MD15[1:8]

Serial communication

interface (SCI)

All registers

—

A/D converter (A/D)

All registers

—

Pin function controller (PFC)

—

All registers

I/O ports (I/O)

—

All registers

Flash memory control

registers

All registers (except RAMER)

—

Power-down state related

—

• Standby control register

(SBYCR)

• System control register

(SYSCR)

• Module stop control register

(MSTCR)

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