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SH7052 Datasheet(PDF) 823 Page - Renesas Technology Corp

Part # SH7052
Description  SuperHTM RISC engine
PDF  919 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Datasheet(HTML) 823 Page - Renesas Technology Corp

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23.2.4
Notes on Register Access
The method of writing to the module standby control register (MSTCR) is different from that of
ordinary registers to prevent inadvertent rewriting.
Be certain to use a word transfer instruction when writing data to MSTCR. Data cannot be written
by a byte transfer instruction. As shown in figure 23.1, set the upper byte to H'3C and transfer data
using the lower byte as write data.
Data can be read by the same method as for ordinary registers.
MSTCR is allocated to address H'FFFFF70A. Always use a byte transfer instruction to read data.
15
8
7
0
H'3C
Write data
Address:
When writing to MSTCR
H'FFFFF70A
Figure 23.1 Writing to MSTCR
23.3
Hardware Standby Mode
23.3.1
Transition to Hardware Standby Mode
The chip enters hardware standby mode when the
HSTBY pin or RES pin goes low. Hardware
standby mode reduces power consumption drastically by halting all SH7052F/SH7053F/SH7054F
functions. As the transition to hardware standby mode is made by means of external pin input, the
transition is made asynchronously, regardless of the current state of the
SH7052F/SH7053F/SH7054F, and therefore the chip state prior to the transition is not preserved.
However, on-chip RAM data is retained as long as the specified voltage is supplied. To retain on-
chip RAM data, clear the RAM enable bit (RAME) to 0 in the system control register (SYSCR)
before driving the
HSTBY pin low. See Appendix B Pin States for the pin states in hardware
standby mode.
23.3.2
Canceling Hardware Standby Mode
Hardware standby mode is canceled by means of the
HSTBY pin and RES pin. When HSTBY is
driven high while
RES is low, the clock oscillator starts running. The RES pin should be held low
long enough for clock oscillation to stabilize. When
RES is driven high, power-on reset exception
processing is started and a transition is made to the program execution state.



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