SH7052 datasheet(821/919 Pages) RENESAS

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23.2.2

System Control Register (SYSCR)

Bit:

—

AUDSRST

RAME

Initial value:

R/W:

R/W

The system control register (SYSCR) is an 8-bit readable/writable register that performs AUD

software reset control and enables or disables access to the on-chip RAM.

SYSCR is initialized to H'01 by a power-on reset.

• Bits 7 to 2—Reserved: These bits always read 0. The write value should always be 0.

• Bit1— AUD Software Reset (AUDSRST): This bit controls AUD reset using software. Setting

the AUDSRST bit to 1 places, the AUD module in the power-on reset state.

Bit 1: AUDSRST Description

AUD reset state cleared

AUD reset state entered

(Initial value)

• Bit 0—RAME Enable (RAME): Selects enabling or disabling of the on-chip RAM. When

RAME is set to 1, on-chip RAM is enabled. When RAME is cleared to 0, on-chip RAM cannot

be accessed. In this case, a read or instruction fetch from on-chip RAM will return an

undefined value, and a write to on-chip RAM will be ignored. The initial value of RAME is 1.

When on-chip RAM is disabled by clearing RAME to 0, do not place an instruction that

attempts to access on-chip RAM immediately after the SYSCR write instruction, as normal

access cannot be guaranteed in this case.

When on-chip RAM is enabled by setting RAME to 1, place an SYSCR read instruction

immediately after the SYSCR write instruction. Normal access cannot be guaranteed if an on-

chip RAM access instruction is placed immediately after the SYSCR write instruction.

Bit 0: RAME

Description

On-chip RAM disabled

On-chip RAM enabled

(Initial value)

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