SH7052 datasheet(818/919 Pages) RENESAS

818 / 919 page

792

Table 23.1 shows the transition conditions for entering the modes from the program execution

state, as well as the CPU and peripheral function status in each mode and the procedures for

canceling each mode.

Table 23.1

Power-Down State Conditions

State

Mode

Entering

Procedure

Clock CPU

CPU

Registers

On-Chip

Peripheral

Modules

RAM

Pins

Canceling

Procedure

Hardware

standby

Low-level

input at

HSTBY pin

Halted Halted Halted

Undefined

Held*

2 Initialized High-level input

HSTBY pin,

executing

power-on reset

Software

standby

Execute

SLEEP

instruction

with SSBY

bit set to 1 in

SBYCR

Halted Halted Held

Halted*

Held

Held or

high

impe-

dance*

• NMI

interrupt

• Power-on

reset

Sleep

Execute

SLEEP

instruction

with SSBY

bit cleared to

0 in SBYCR

Runs

Halted Held

Run

Held

• Interrupt

• DMA

address

error

• Power-on

reset

• Manual

reset

Notes: SBYCR: Standby control register

SSBY: Software standby bit

1. Some bits within on-chip peripheral module registers are initialized in software standby

mode, and some are not. See table 23.4, Register States in Software Standby Mode.

Also refer to the register descriptions for each peripheral module.

2. Clear the RAME bit of the SYSCR to 0 in advance when changing the state from the

program execution state to the hardware standby state.

3. The state of the I/O ports in standby mode is set by the port high impedance bit (HIZ) in

SBYCR. See section 23.2.1, Standby Control Register (SBYCR). For details of other

pin states, refer to Appendix B Pin States.

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