SH7052 datasheet(850/919 Pages) RENESAS

850 / 919 page

824

24.3.3

Control Signal Timing

Table 24.8 shows control signal timing.

Table 24.8

Control Signal Timing

Conditions: V

CC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,

CC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC,

SS = PLLVSS = AVSS = 0 V, Ta = –40°C to 85°C.

When PV

CC1 = 3.3 V ±0.3 V, VCC = PVCC1.

When writing or erasing flash EEPROM, T

a = –40°C to 85°C.

Item

Symbol

Min

Max

Unit

Figures

RES pulse width

RESW

—

cyc

Figure 24.5

RES setup time

RESS

—

MD2 to MD0 setup time

MDS

—

cyc

NMI setup time

NMIS

—

Figure 24.6

IRQ3 to IRQ0 setup time*

1 (edge detection)

IRQES

—

IRQ3 to IRQ0 setup time*

1 (level detection)

IRQLS

—

NMI hold time

NMIH

—

IRQ3 to IRQ0 hold time

IRQEH

—

Bus request setup time

BRQS

—

Figure 24.7

Bus acknowledge delay time 1

BACKD1

—

Bus acknowledge delay time 2

BACKD2

—

Bus three-state delay time

BZD

—

[Operating precautions]

The operation guaranteed voltage range of power supply PV

CC1 in MCU expansion mode is 3.3 V

±0.3 V. Do not use a voltage outside this range.

*1 The

RES, NMI and IRQ3 to IRQ0 signals are asynchronous inputs, but when the setup times

shown here are provided, the signals are considered to have been changed at clock fall. If the

setup times are not provided, recognition is delayed until the next clock rise or fall.

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