SH7052 datasheet(866/919 Pages) RENESAS

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24.3.11

AUD Timing

Table 24.16 shows AUD timing.

Table 24.16 AUD Timing

Conditions: V

CC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,

CC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC,

SS = PLLVSS = AVSS = 0 V, Ta = –40°C to 85°C.

When PV

CC1 = 3.3 V ±0.3 V, VCC = PVCC1.

When writing or erasing flash EEPROM, T

a = –40°C to 85°C.

Item

Symbol

Min

Max

Unit

Figures

AUDRST pulse width (Branch trace

mode)

AUDRSTW

—

cyc

Figure 24.20

AUDRST pulse width (RAM monitor

mode)

AUDRSTW

—

RMCYC

AUDMD setup time (Branch trace mode)

AUDMDS

—

cyc

AUDMD setup time (RAM monitor mode) t

AUDMDS

—

RMCYC

Branch trace clock cycle

RTCYC

cyc

Figure 24.21

Branch trace clock duty

RTCKW

Branch trace data delay time

RTDD

—

Branch trace data hold time

RTDH

—

Branch trace SYNC delay time

RTSD

—

Branch trace SYNC hold time

RTSH

—

RAM monitor clock cycle

RMCYC

100

—

Figure 24.22

RAM monitor clock low pulse width

RMCKW

—

RAM monitor output data delay time

RMDD

RMCYC – 20

RAM monitor output data hold time

RMDHD

—

RAM monitor input data setup time

RMDS

—

RAM monitor input data hold time

RMDH

—

RAM monitor SYNC setup time

RMSS

—

RAM monitor SYNC hold time

RMSH

—

Load conditions: AUDCK (in branch trace): C

L = 30 pF: Other than above CL = 100 pF

AUDSYNC, AUDATA3 to AUDATA0: C

L = 100 pF

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