SH7052 datasheet(271/919 Pages) RENESAS

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• Bit 15—Reserved: This bit always reads 0. The write value should always be 0.

• Bit 14—Overflow Flag 5 (OVF5): Status flag that indicates TCNT5 overflow.

Bit 14: OVF5

Description

[Clearing condition]

(Initial value)

When OVF5 is read while set to 1, then 0 is written to OVF5

[Setting condition]

When the TCNT5 value overflows (from H'FFFF to H'0000)

• Bit 13—Input Capture/Compare-Match Flag 5D (IMF5D): Status flag that indicates GR5D

input capture or compare-match.

Bit 13: IMF5D

Description

[Clearing condition]

(Initial value)

When IMF5D is read while set to 1, then 0 is written to IMF5D

[Setting conditions]

• When the TCNT5 value is transferred to GR5D by an input capture signal

while GR5D is functioning as an input capture register

•••• When TCNT5 = GR5D while GR5D is functioning as an output compare

•••• When TCNT5 = GR5D while GR5D is functioning as a synchronous

• Bit 12—Input Capture/Compare-Match Flag 5C (IMF5C): Status flag that indicates GR5C

input capture or compare-match. The flag is not set in PWM mode.

Bit 12: IMF5C

Description

[Clearing condition]

(Initial value)

When IMF5C is read while set to 1, then 0 is written to IMF5C

[Setting conditions]

• When the TCNT5 value is transferred to GR5C by an input capture signal

while GR5C is functioning as an input capture register

•••• When TCNT5 = GR5C while GR5C is functioning as an output compare

SH7052 Datasheet(PDF) 271 Page - Renesas Technology Corp