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SH7052 Datasheet(PDF) 272 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 272 Page - Renesas Technology Corp |
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272 / 919 page ![]() 246 • Bit 11—Input Capture/Compare-Match Flag 5B (IMF5B): Status flag that indicates GR5B input capture or compare-match. The flag is not set in PWM mode. Bit 11: IMF5B Description 0 [Clearing condition] (Initial value) When IMF5B is read while set to 1, then 0 is written to IMF5B 1 [Setting conditions] • When the TCNT5 value is transferred to GR5B by an input capture signal while GR5B is functioning as an input capture register •••• When TCNT5 = GR5B while GR5B is functioning as an output compare register • Bit 10—Input Capture/Compare-Match Flag 5A (IMF5A): Status flag that indicates GR5A input capture or compare-match. The flag is not set in PWM mode. Bit 10: IMF5A Description 0 [Clearing condition] (Initial value) When IMF5A is read while set to 1, then 0 is written to IMF5A 1 [Setting conditions] • When the TCNT5 value is transferred to GR5A by an input capture signal while GR5A is functioning as an input capture register •••• When TCNT5 = GR5A while GR5A is functioning as an output compare register • Bit 9—Overflow Flag 4 (OVF4): Status flag that indicates TCNT4 overflow. Bit 9: OVF4 Description 0 [Clearing condition] (Initial value) When OVF4 is read while set to 1, then 0 is written to OVF4 1 [Setting condition] When the TCNT4 value overflows (from H'FFFF to H'0000) |
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