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SH7052 Datasheet(PDF) 276 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 276 Page - Renesas Technology Corp |
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276 / 919 page ![]() 250 Timer Status Registers 6 and 7 (TSR6, TSR7) TSR6 and TRS7 indicate the channel 6 and 7 free-running counter up-count and down-count status, and cycle register compare status. Bit: 15 14 13 12 11 10 9 8 —— —— ——— — Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 UDxD UDxC UDxB UDxA CMFxD CMFxC CMFxB CMFxA Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. x = 6 or 7 UDxA to UDxD relate to TSR6 only. Bits relating to TSR7 always read 0. • Bits 15 to 8—Reserved: These bits always read 0. The write value should always be 0. • Bit 7—Count-Up/Count-Down Flag 6D (UD6D): Status flag that indicates the TCNT6D count operation. Bit 7: UD6D Description 0 Free-running counter TCNT6D operates as an up-counter 1 Free-running counter TCNT6D operates as a down-counter • Bit 6—Count-Up/Count-Down Flag 6C (UD6C): Status flag that indicates the TCNT6C count operation. Bit 6: UD6C Description 0 Free-running counter TCNT6C operates as an up-counter 1 Free-running counter TCNT6C operates as a down-counter |
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