SH7052 datasheet(316/919 Pages) RENESAS

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10.2.11

Down-Count Start Register (DSTR)

The down-count start register (DSTR) is a 16-bit register. The ATU-II has one DSTR register in

channel 8.

Bit:

DST8P

DST8O

DST8N

DST8M

DST8L

DST8K

DST8J

DST8I

Initial value:

R/W:

R/W*

Bit:

DST8H

DST8G

DST8F

DST8E

DST8D

DST8C

DST8B

DST8A

Initial value:

R/W:

R/W*

Note: * Only 1 can be written.

DSTR is a 16-bit readable/writable register that starts the channel 8 down-counter (DCNT).

When the one-shot pulse function is used, a value of 1 can be set in a DST8x bit at any time by the

user program, except when the corresponding DCNT8x value is H'0000. The DST8x bits are

cleared to 0 automatically when the DCNT value overflows.

When the offset one-shot pulse function is used, DST8x is automatically set to 1 (except when the

DCNT8x value is H'0000) when a compare-match occurs between the channel 1 or 2 free-running

counter (TCNT) and a general register (GR) or the output compare register (OCR1) while the

corresponding timer connection register (TCNR) bit is set to 1. As regards DST8I to DST8P, if the

RLDEN bit in the reload enable register (RLDENR) is set to 1 and the reload register (RLDR8)

value is not H'0000, a reload is performed into the corresponding DCNT8x, and the DST8x bit is

set to 1. DST8x is automatically cleared to 0 when the DCNT8x value underflows, or by input of a

channel 1 or 2 one-shot terminate trigger signal set in the trigger mode register (TRGMDR) while

the corresponding one-shot pulse terminate register (OTR) bit is set to 1, whichever occurs first.

DCNT8x is cleared to H'0000 when underflow occurs.

DSTR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software

standby mode.

For details, see sections 10.3.5, One-Shot Pulse Function, and 10.3.6, Offset One-Shot Pulse

Function and Output Cutoff Function.

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