SH7052 datasheet(312/919 Pages) RENESAS

312 / 919 page

286

10.2.8

Trigger Mode Register (TRGMDR)

The trigger mode register (TRGMDR) is an 8-bit register. The ATU-II has one TRGMDR register.

Bit:

TRGMD

——

—

Initial value:

R/W:

R/W

TRGMDR is an 8-bit readable/writable register that selects whether a channel 1 compare-match is

used as a channel 8 one-shot pulse start trigger or as a one-shot pulse terminate trigger when

channel 1 and channel 8 are used in combination.

TRGMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software

standby mode.

• Bit 7—Trigger Mode Selection Register (TRGMD): Selects the channel 8 one-shot pulse start

trigger/one-shot pulse terminate trigger setting.

Bit 7: TRGMD

Description

One-shot pulse start trigger (TCNT1B = OCR1)

(Initial value)

One-shot pulse terminate trigger (TCNT1A = GR1A to GR1H)

One-shot pulse start trigger (TCNT1A = GR1A to GR1H)

One-shot pulse terminate trigger (TCNT1B = OCR1)

• Bits 6 to 0—Reserved: These bits always read 0. The write value should always be 0.

10.2.9

Timer Mode Register (TMDR)

The timer mode register (TMDR) is an 8-bit register. The ATU-II has one TDR register.

Bit:

——

—

T5PWM T4PWM T3PWM

Initial value:

R/W:

R/W

TMDR is an 8-bit readable/writable register that specifies whether channels 3 to 5 are used in

input capture/output compare mode or PWM mode.

TMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software

standby mode.

SH7052 Datasheet(PDF) 312 Page - Renesas Technology Corp