SH7052 datasheet(308/919 Pages) RENESAS

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10.2.7

Interval Interrupt Request Registers (ITVRR)

The interval interrupt request registers (ITVRR) are 8-bit registers. The ATU-II has three ITVRR

registers in channel 0.

Channel

Abbreviation

Function

ITVRR1

TCNT0 bit 6 to 9 interval interrupt generation

ITVRR2A

TCNT0 bit 10 to 13 interval interrupt generation and A/D0

converter activation

ITVRR2B

TCNT0 bit 10 to 13 interval interrupt generation and A/D1

converter activation

Interval Interrupt Request Register 1 (ITVRR1)

Bit:



ITVE9

ITVE8

ITVE7

ITVE6

Initial value:

R/W:

R/W

ITVRR1 is an 8-bit readable/writable register that detects the rise of bits corresponding to the

channel 0 free-running counter (TCNT0) and requests cyclic interrupt.

ITVRR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software

standby mode.

• Bit 7 to 4—Reserved: These bits always read 0. The write value should always be 0.

• Bit 3—Interval Interrupt Bit 9 (ITVE9): INTC interval interrupt setting bit corresponding to bit

9 in TCNT0. The rise of bit 9 in TCNT0 is ANDed with ITVE9, the result is stored in IIF1 in

TSR0, and an interrupt request is sent to the CPU.

Bit 3: ITVE9

Description

Interrupt request (ITV1) by rise of TCNT0 bit 9 is disabled

(Initial value)

Interrupt request (ITV1) by rise of TCNT0 bit 9 is enabled

• Bit 2—Interval Interrupt Bit 8 (ITVE8): INTC interval interrupt setting bit corresponding to bit

8 in TCNT0. The rise of bit 8 in TCNT0 is ANDed with ITVE8, the result is stored in IIF1 in

TSR0, and an interrupt request is sent to the CPU.

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