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SH7052 Datasheet(PDF) 332 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 332 Page - Renesas Technology Corp |
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332 / 919 page ![]() 306 10.2.15 Free-Running Counters (TCNT) The free-running counters (TCNT) are 32- or 16-bit up- or up/down-counters. The ATU-II has 17 TCNT counters: one 32-bit TCNT in channel 0, and sixteen 16-bit TCNTs in each of channels 1 to 7 and 11. Channel Abbreviation Function 0 TCNT0H, TCNT0L 32-bit up-counter (initial value H’00000000) 1 TCNT1A, TCNT1B 16-bit up-counters (initial value H'0000) 2 TCNT2A, TCNT2B 3 TCNT3 4 TCNT4 5 TCNT5 6 TCNT6A to TCNT6D 16-bit up/down-counters (initial value H'0001) 7 TCNT7A to TCNT7D 16-bit up-counters (initial value H'0001) 11 TCNT11 16-bit up-counter (initial value H'0000) Free-Running Counter 0 (TCNT0H, TCNT0L): Free-running counter 0 (comprising TCNT0H and TCNT0L) is a 32-bit readable/writable register that counts on an input clock. When the bits corresponding to the timer start register 1 (TSTR1) are set to 1, this counter starts to count. The input clock is selected with prescaler register 1 (PSCR1). Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When TCNT0 overflows (from H'FFFFFFFF to H'00000000), the OVF0 overflow flag in the timer status register (TSR0) is set to 1. TCNT0 can only be accessed by a longword read or write. Word reads or writes cannot be used. TCNT0 is initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode. |
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