3820 datasheet(49/349 Pages) RENESAS

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3820 GROUP USER’S MANUAL

1-32

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

LCD DRIVE CONTROL CIRCUIT

The 3820 group has the built-in Liquid Crystal Display (LCD) drive

control circuit consisting of the following.

•LCD display RAM

•Segment output enable register

•LCD mode register

•Selector

•Timing controller

•Common driver

•Segment driver

•Bias control circuit

A maximum of 40 segment output pins and 4 common output pins

can be used.

Up to 160 pixels can be controlled for LCD display. When the LCD

enable bit is set to “1” after data is set in the LCD mode register,

Fig. 30 Structure of segment output enable register and LCD mode register

Segment output enable register

(SEG : address 003816)

LCD mode register

(LM : address 003916)

Duty ratio selection bits

0 0 : Not available

0 1 : 2 (use COM0,COM1)

1 0 : 3 (use COM0–COM2)

1 1 : 4 (use COM0–COM3)

Bias control bit

0 : 1/3 bias

1 : 1/2 bias

LCD enable bit

0 : LCD OFF

1 : LCD ON

Not used (returns "0" when read)

(Do not write "1" to this bit)

LCD circuit divider division ratio selection bits

0 0 : LCDCK count source

0 1 : 2 division of LCDCK count source

1 0 : 4 division of LCDCK count source

1 1 : 8 division of LCDCK count source

LCDCK count source selection bit (Note)

0 : f(XCIN)/32

1 : f(XIN)/8192

Segment output enable bit 0

0 : Input ports P30–P37

1 : Segment output SEG16–SEG23

Segment output enable bit 1

0 : I/O ports P00, P01

1 : Segment output SEG 24,SEG25

Segment output enable bit 2

0 : I/O ports P02–P07

1 : Segment output SEG26–SEG31

Segment output enable bit 3

0 : I/O ports P10,P11

1 : Segment output SEG32,SEG33

Segment output enable bit 4

0 : I/O port P12

1 : Segment output SEG34

Segment output enable bit 5

0 : I/O ports P13–P17

1 : Segment output SEG35–SEG39

Not used (return "0" when read)

(Do not write "1" to this bit)

Note : LCDCK is a clock for a LCD timing controller.

the segment output enable register and the LCD display RAM, the

LCD drive control circuit starts reading the display data automati-

cally, performs the bias control and the duty ratio control, and dis-

plays the data on the LCD panel.

Table 8. Maximum number of display pixels at each

duty ratio

Duty ratio

Maximum number of display pixel

80 dots

or 8 segment LCD 10 digits

120 dots

or 8 segment LCD 15 digits

160 dots

or 8 segment LCD 20 digits

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