SH7243 datasheet(587/1726 Pages) RENESAS

587 / 1726 page

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 1.00 Jun. 26, 2008 Page 557 of 1692

REJ09B0393-0100

(1)

Example of Complementary PWM Mode Setting Procedure

An example of the complementary PWM mode setting procedure is shown in figure 11.38.

Complementary PWM mode

Stop count operation

Counter clock, counter clear

source selection

Brushless DC motor control

setting

TCNT setting

Inter-channel synchronization

setting

TGR setting

Enable/disable dead time

generation

Start count operation

[1] Clear bits CST3 and CST4 in the timer start register

(TSTR) to 0, and halt timer counter (TCNT) operation.

Perform complementary PWM mode setting when

TCNT_3 and TCNT_4 are stopped.

[2] Set the same counter clock and clock edge for channels

3 and 4 with bits TPSC2-TPSC0 and bits CKEG1 and

CKEG0 in the timer control register (TCR). Use bits

CCLR2-CCLR0 to set synchronous clearing only when

restarting by a synchronous clear from another channel

during complementary PWM mode operation.

[3] When performing brushless DC motor control, set bit BDC

in the timer gate control register (TGCR) and set the

feedback signal input source and output chopping or gate

signal direct output.

[4] Set the dead time in TCNT_3. Set TCNT_4 to H'0000.

[5] Set only when restarting by a synchronous clear from

another channel during complementary PWM mode

operation. In this case, synchronize the channel generating

the synchronous clear with channels 3 and 4 using the timer

synchro register (TSYR).

[6] Set the output PWM duty in the duty registers (TGRB_3,

TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4,

TGRD_4). Set the same initial value in each corresponding

TGR.

[7] This setting is necessary only when no dead time should be

generated. Make appropriate settings in the timer dead time

enable register (TDER) so that no dead time is generated.

[8] Set the dead time in the dead time register (TDDR), 1/2 the

carrier cycle in the carrier cycle data register (TCDR) and

carrier cycle buffer register (TCBR), and 1/2 the carrier cycle

plus the dead time in TGRA_3 and TGRC_3. When no dead

time generation is selected, set 1 in TDDR and 1/2 the carrier

cycle + 1 in TGRA_3 and TGRC_3.

[9] Select enabling/disabling of toggle output synchronized with

the PWM cycle using bit PSYE in the timer output control

and OLSN. When specifying the PWM output level by using

TOLBR as a buffer for TOCR_2, see figure 10.3.

[10] Select complementary PWM mode in timer mode register 3

(TMDR_3). Do not set in TMDR_4.

[11] Set enabling/disabling of PWM waveform output pin output in

the timer output master enable register (TOER).

[12] Set the port control register and the port I/O register.

[13] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start

the count operation.

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[11]

Dead time, carrier cycle

setting

PWM cycle output enabling,

PWM output level setting

Complementary PWM mode

setting

Enable waveform output

Start count operation

[10]

PFC setting

[12]

[13]

Figure 11.38 Example of Complementary PWM Mode Setting Procedure

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