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SH7243 Datasheet(PDF) 21 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 21 Page - Renesas Technology Corp

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Rev. 1.00 Jun. 26, 2008 Page xxi of xxx
17.4.3
Operation in Clocked Synchronous Mode ........................................................ 866
17.5
SCIF Interrupts .................................................................................................................875
17.6
Usage Notes ...................................................................................................................... 876
17.6.1
SCFTDR Writing and TDFE Flag .................................................................... 876
17.6.2
SCFRDR Reading and RDF Flag ..................................................................... 876
17.6.3
Restriction on DMAC and DTC Usage ............................................................ 877
17.6.4
Break Detection and Processing ....................................................................... 877
17.6.5
Sending a Break Signal..................................................................................... 877
17.6.6
Receive Data Sampling Timing and Receive Margin
(Asynchronous Mode)....................................................................................... 878
17.6.7
FER Flag and PER Flag of Serial Status Register (SCFSR)............................. 879
Section 18 Synchronous Serial Communication Unit (SSU) ..............................881
18.1
Features............................................................................................................................. 881
18.2
Input/Output Pins.............................................................................................................. 883
18.3
Register Descriptions ........................................................................................................ 884
18.3.1
SS Control Register H (SSCRH) ...................................................................... 885
18.3.2
SS Control Register L (SSCRL) ....................................................................... 887
18.3.3
SS Mode Register (SSMR) ............................................................................... 888
18.3.4
SS Enable Register (SSER) .............................................................................. 889
18.3.5
SS Status Register (SSSR) ................................................................................ 891
18.3.6
SS Control Register 2 (SSCR2) ........................................................................ 894
18.3.7
SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)............................... 896
18.3.8
SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3) ................................ 897
18.3.9
SS Shift Register (SSTRSR) ............................................................................. 898
18.4
Operation .......................................................................................................................... 899
18.4.1
Transfer Clock .................................................................................................. 899
18.4.2
Relationship of Clock Phase, Polarity, and Data .............................................. 899
18.4.3
Relationship between Data Input/Output Pins and Shift Register .................... 900
18.4.4
Communication Modes and Pin Functions ....................................................... 902
18.4.5
SSU Mode......................................................................................................... 904
18.4.6
SCS Pin Control and Conflict Error.................................................................. 914
18.4.7
Clock Synchronous Communication Mode ...................................................... 916
18.5
SSU Interrupt Sources and DTC or DMAC...................................................................... 923
18.6
Usage Notes ...................................................................................................................... 924
18.6.1
Module Standby Mode Setting ......................................................................... 924
18.6.2
Access to SSTDR and SSRDR Registers.......................................................... 924
18.6.3
Continuous Transmission/Reception in SSU Slave Mode ................................ 924
18.6.4
Note for Reception Operations in SSU Slave Mode ......................................... 924



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