SH7243 datasheet(26/1726 Pages) RENESAS

26 / 1726 page

Rev. 1.00 Jun. 26, 2008 Page xxvi of xxx

25.3.9

USBEP0s Data Register (USBEPDR0s)......................................................... 1335

25.3.10

USBEP1 Data Register (USBEPDR1)............................................................ 1336

25.3.11

USBEP2 Data Register (USBEPDR2)............................................................ 1337

25.3.12

USBEP3 Data Register (USBEPDR3)............................................................ 1338

25.3.13

USBEP0o Receive Data Size Register (USBEPSZ0o) ................................... 1338

25.3.14

USBEP1 Receive Data Size Register (USBEPSZ1) ....................................... 1339

25.3.15

USB Trigger Register (USBTRG) .................................................................. 1340

25.3.16

USB Data Status Register (USBDASTS) ....................................................... 1342

25.3.17

USBFIFO Clear Register (USBFCLR)........................................................... 1343

25.3.18

USBDMA Transfer Setting Register (USBDMAR) ....................................... 1344

25.3.19

USB Endpoint Stall Register (USBEPSTL) ................................................... 1346

25.4

Interrupt Sources............................................................................................................. 1347

25.5

Operation ........................................................................................................................ 1349

25.5.1

Cable Connection............................................................................................ 1349

25.5.2

Cable Disconnection ....................................................................................... 1350

25.5.3

Control Transfer.............................................................................................. 1351

25.5.4

EP1 Bulk-OUT Transfer (Dual FIFOs) .......................................................... 1357

25.5.5

EP2 Bulk-IN Transfer (Dual FIFOs) .............................................................. 1358

25.5.6

EP3 Interrupt-IN Transfer............................................................................... 1360

25.6

Processing of USB Standard Commands and Class/Vendor Commands ....................... 1361

25.6.1

Processing of Commands Transmitted by Control Transfer ........................... 1361

25.7

Stall Operations .............................................................................................................. 1362

25.7.1

Forcible Stall by Application .......................................................................... 1362

25.7.2

Automatic Stall by USB Function Module ..................................................... 1364

25.8

DMA Transfer ................................................................................................................ 1365

25.8.1

DMA Transfer for Endpoint 1 ........................................................................ 1365

25.8.2

DMA Transfer for Endpoint 2 ........................................................................ 1368

25.9

DTC Transfer.................................................................................................................. 1371

25.9.1

DTC Transfer for Endpoint 1.......................................................................... 1371

25.9.2

DTC Transfer for Endpoint 2.......................................................................... 1374

25.10 Example of USB External Circuitry ............................................................................... 1377

25.11 Notes on Usage ............................................................................................................... 1378

25.11.1

Receiving Setup Data...................................................................................... 1378

25.11.2

Clearing FIFO................................................................................................. 1378

25.11.3

Overreading or Overwriting Data Register ..................................................... 1378

25.11.4

Assigning Interrupt Source for EP0 ................................................................ 1379

25.11.5

Clearing FIFO when Setting DMA/DTC Transfer ......................................... 1379

25.11.6

Manual Reset for DMA/DTC Transfer........................................................... 1379

25.11.7

USB Clock ...................................................................................................... 1379

25.11.8

Using TR Interrupt.......................................................................................... 1379

SH7243 Datasheet(PDF) 26 Page - Renesas Technology Corp

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