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SH7243 Datasheet(PDF) 613 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 613 Page - Renesas Technology Corp |
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613 / 1726 page  Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 1.00 Jun. 26, 2008 Page 583 of 1692 REJ09B0393-0100 (o) Suppressing MTU2-MTU2S Synchronous Counter Clearing In the MTU2S, setting the SCC bit in TWCR to 1 suppresses synchronous counter clearing caused by the MTU2. Synchronous counter clearing is suppressed only within the interval shown in figure 11.62. When using this function, the MTU2S should be set to complementary PWM mode. For details of synchronous clearing caused by the MTU2, refer to the description about MTU2S counter clearing caused by MTU2 flag setting source (MTU2-MTU2S synchronous counter clearing) in section 11.4.10, MTU2-MTU2S Synchronous Operation. Tb interval at the crest Tb interval at the trough Tb interval at the crest Tb interval at the trough TGRA_3 TGRB_3 TCDR TDDR H'0000 Tb interval immediately after counter operation starts MTU2-MTU2S synchronous counter clearing is suppressed. MTU2-MTU2S synchronous counter clearing is suppressed. Figure 11.62 MTU2-MTU2S Synchronous Clearing-Suppressed Interval Specified by SCC Bit in TWCR |
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