SH7243 datasheet(162/1726 Pages) RENESAS

162 / 1726 page

Section 6 Interrupt Controller (INTC)

Rev. 1.00 Jun. 26, 2008 Page 132 of 1692

REJ09B0393-0100

6.3.7

USB-DTC Transfer Interrupt Request Register (USDTENDRR)

USDTENDRR is a 16-bit register that indicates USB-DTC transfer end interrupt requests, which

are on-chip peripheral module interrupts. Writing 0 to the RXF or TXF bit after reading RXF = 1

or TXF = 1 cancels the retained interrupt.

USDTENDRR is initialized by a power-on reset.

00000000

R/(W)* R/(W)*

00000000

RRRRRR

RXF

TXF

------

-------

Note:

Only 0 can be written to clear the flag after 1 is read.

Bit:

Initial value:

R/W:

Bit

Bit Name

Initial

Value

R/W

Description

RXF

R/(W)*

EP1-FIFO Full DTC Transfer End Interrupt Request

0: EP1-FIFO full DTC transfer end interrupt request has

not occurred

[Clearing conditions]

• Cleared by reading RFX = 1, then writing 0 to RFX

• Cleared by executing EP1-FIFO full DTC transfer

end interrupt exception handling

1: EP1-FIFO full DTC transfer end interrupt request has

occurred

TXF

R/(W)*

EP2-FIFO Empty DTC Transfer End Interrupt Request

0: EP2-FIFO empty DTC transfer end interrupt request

has not occurred

[Clearing conditions]

• Cleared by reading TFX = 1, then writing 0 to TFX

• Cleared by executing EP2-FIFO empty DTC

transfer end interrupt exception handling

1: EP2-FIFO empty DTC transfer end interrupt request

has occurred

13 to 0



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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