SH7243 datasheet(192/1726 Pages) RENESAS

192 / 1726 page

Section 6 Interrupt Controller (INTC)

Rev. 1.00 Jun. 26, 2008 Page 162 of 1692

REJ09B0393-0100

6.9.1

Handling Interrupt Request Signals as DTC Activating Sources and CPU Interrupt

Sources but Not as DMAC Activating Sources

1. Do not select DMAC activating sources or clear the DME bit to 0. If, DMAC activating

sources are selected, clear the DE bit to 0 for the relevant channel of the DMAC.

2. Set both the corresponding DTCE bit and DISEL bit to 1 in the DTC.

3. Activating sources are applied to the DTC when interrupts occur.

4. The DTC clears the DTCE bit to 0 and sends interrupt requests to the CPU when starting data

transfer. The DTC does not clear the activating sources.

5. The CPU clears the interrupt sources in the interrupt exception handling routine, and then

confirms the transfer counter value. If the transfer counter value is not 0, the DTCE bit is set to

1 and the next data transfer enabled. If the transfer counter value is 0, the CPU performs the

necessary termination processing in the interrupt exception handling routine.

6.9.2

Handling Interrupt Request Signals as DMAC Activating Sources but Not as CPU

Interrupt Sources

1. Select DMAC activating sources and set both the DE and DME bits to 1. This masks CPU

interrupt sources regardless of the interrupt priority register and DTC register settings.

2. Activating sources are applied to the DMAC when interrupts occur.

3. The DMAC clears the activating sources when starting data transfer.

6.9.3

Handling Interrupt Request Signals as DTC Activating Sources but Not as CPU

Interrupt Sources or DMAC Activating Sources

1. Do not select DMAC activating sources or clear the DME bit to 0. If, DMAC activating

sources are selected, clear the DE bit to 0 for the relevant channel of the DMAC.

2. Set the corresponding DTCE bit to 1 and clear the DISEL bit to 0 in the DTC.

3. Activating sources are applied to the DTC when interrupts occur.

4. The DTC clears the activating sources when starting data transfer. Interrupt requests are not

sent to the CPU because the DTCE bit remains set to 1.

5. However, when the transfer counter value is 0, the DTCE bit is cleared to 0 and interrupt

requests are sent to the CPU.

6. The CPU performs the necessary termination processing in the interrupt exception handling

routine.

SH7243 Datasheet(PDF) 192 Page - Renesas Technology Corp