SH7243 datasheet(199/1726 Pages) RENESAS

199 / 1726 page

Section 7 User Break Controller (UBC)

Rev. 1.00 Jun. 26, 2008 Page 169 of 1692

REJ09B0393-0100

7.3.1

Break Address Register_0 (BAR_0)

BAR_0 is a 32-bit readable/writable register. BAR_0 specifies the address used as a break

condition in channel 0. The control bits CD0_1 and CD0_0 in the break bus cycle register_0

(BBR_0) select one of the three address buses for a break condition of channel 0. BAR_0 is

initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or

in software standby mode or sleep mode.

0000000000000000

R/W

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

BA0_31 BA0_30 BA0_29 BA0_28 BA0_27 BA0_26 BA0_25 BA0_24 BA0_23 BA0_22 BA0_21 BA0_20 BA0_19 BA0_18 BA0_17 BA0_16

BA0_15 BA0_14 BA0_13 BA0_12 BA0_11 BA0_10 BA0_9 BA0_8 BA0_7 BA0_6 BA0_5 BA0_4 BA0_3 BA0_2 BA0_1 BA0_0

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

BA0_31 to

BA0_0

All 0

R/W

Break Address 0

Store an address on the CPU address bus (FAB or

MAB) or IAB specifying break conditions of channel 0.

When the C bus and instruction fetch cycle are

selected by BBR_0, specify an FAB address in bits

BA0_31 to BA0_0.

When the C bus and data access cycle are selected by

BBR_0, specify an MAB address in bits BA0_31 to

BA0_0.

Note:

When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_0 to 0.

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