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SH7243 Datasheet(PDF) 311 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 311 Page - Renesas Technology Corp |
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311 / 1726 page  Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 281 of 1692 REJ09B0393-0100 Bit Bit Name Initial Value R/W Description Burst Count Specification Specify the burst count for 16-byte access. These bits must not be set to B'11. Bus Width BST[1:0] Burst count 00 16 burst × one time 8 bits 01 4 burst × four times 00 8 burst × one time 01 2 burst × four times 16 bits 10 4-4 or 2-4-2 burst 21, 20 BST[1:0] 00 R/W 19, 18 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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