SH7706 datasheet(97/749 Pages) RENESAS

97 / 749 page

Section 2 CPU

Rev. 5.00 May 29, 2006 page 49 of 698

REJ09B0146-0500

2.5

Processor States and Processor Modes

2.5.1

Processor States

The SH7706 has five processor states: the reset state, exception-handling state, bus-released state,

program execution state, and power-down state.

Reset State: In this state the CPU is reset. The CPU enters the power-on reset state if the

RESETP

pin is low, or the manual reset state if the

RESETM pin is low. See section 4, Exception

Processing, for more information on resets.

In the power-on reset state, the internal states of the CPU and the on-chip supporting module

registers are initialized. In the manual reset state, the internal states of the CPU and registers of on-

chip supporting modules other than the bus state controller (BSC) are initialized. For details, refer

to section 23.3, Register States in Processing Mode.

Exception-Handling State: This is a transient state during which the CPU's processor state flow

is altered by a reset, general exception, or interrupt exception handling.

In the case of a reset, the CPU branches to address H'A0000000 and starts executing the user-

coded exception handling program.

In the case of a general exception or interrupt, the program counter (PC) contents are saved in the

saved program counter (SPC) and the status register (SR) contents are saved in the saved status

found from the sum of the contents of the vector base address and the vector offset. See section 4,

Exception Processing, for more information on resets, general exceptions, and interrupts.

Program Execution State: In this state the CPU executes program instructions in sequence.

Power-Down State: In the power-down state, CPU operation halts and power consumption is

reduced. There are three modes in the power-down state: sleep mode, software standby mode and

hardware standby mode. The software standby mode and hardware standby mode are expressed by

a generlc name, standby mode. See section 22, Power-Down Modes, for more information.

Bus-Released State: In this state the CPU has released the bus to a device that requested it.

Transitions between the states are shown in figure 2.6.

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