7540 datasheet(203/366 Pages) RENESAS

203 / 366 page

2-127

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

7540 Group

APPLICATION

2.7 Serial I/O2

Fig. 2.7.12 Control procedure of reception side

0 11

RESET

0 00

SIO2(Address 3116)

Set dummy data to serial I/O2 register

(Note 1)

Wait for half cycle of clock (Note 2)

SIO2(Address 3116)

Read receive data from serial I/O2 register

SIO2(Address 3116)

Set quasi-SRDY signal port P00 to the output mode.

SIO2CON(Address 3016)

Synchronous clock: f(XIN)/64

SDATA2 pin: SDATA2 input

LSB first

SCLK2 pin: External clock

Set serial I/O2 control register

2 ms elapsed ?

(generated by timer)

Initialization

SEI

CLD

CLT

Set dummy data to the serial I/O2 register

(Note 1)

Receive has completed?

(checked by b7 of SIO2CON

(address 3016))

Set port P12 to the input mode.

Notes 1: The transmit/receive shift completion flag of the serial I/O2 control register is “1” after

transmit/receive shift is completed. In order to set “0” to this flag, set data (dummy data at

receive) to the serial I/O2 register by program.

2: Bit 7 (transmit/receive shift completion flag) of the serial I/O2 control register is set earlier

than the completion of the actual shift operation for a half cycle of shift clock. Accordingly,

when the shift completion is checked by using this bit, read/write the serial I/O2 register after

a half or more cycle of clock from the setting “1” to this bit is checked.

Output “1” from quasi-SRDY signal port P00.

Set port P13 to the input mode.

Receive has completed?

(checked by b7 of SIO2CON

(address 3016))

Wait for half cycle of clock (Note 2)

Read receive data from serial I/O2 register

Output “0” from quasi-SRDY signal port P00.

Output “1” from quasi-SRDY signal port P00.

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