7540 datasheet(306/366 Pages) RENESAS

306 / 366 page

3-84

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

APPENDIX

7540 Group

3.3 Notes on use

➂ When the on-chip oscillation is used as the operation clock, the CPU clock division ratio is the

middle-speed mode.

➃ When the state transition state 2

→state 3→state 4 is performed, execute the NOP instruction as

shown below according to the division ratio of CPU clock.

• CPUM76

→102 (State 2→state 3)

• NOP instruction

• CPUM4

→12 (State 3→state 4)

Double-speed mode at on-chip oscillator: NOP✕3

High-speed mode at on-chip oscillator: NOP✕1

Middle-speed mode at on-chip oscillator: NOP✕0

(6) Switch of ceramic and RC oscillations

After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic oscillation

or an RC oscillation is selected by setting bit 5 of the CPU mode register.

(7) Double-speed mode

When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an

RC oscillation is selected.

(8) Clock division ratio, XIN oscillation control, on-chip oscillator control

The state transition shown in Figure 3.3.3 can be performed by setting the clock division ratio

selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit

(bit 3) of CPU mode register. Be careful of notes on use in Figure 3.3.3.

Fig. 3.3.3 State transition

Stop mode

Wait mode

WIT

instruction

Oscillation stop detection circuit valid

CPUM4

←12

MISRG1

←12

Interrupt

STP

instruction

WIT

instruction

Interrupt

MISRG1

←02

CPUM3

←12

CPUM3

←02

CPUM76

←102

CPUM76

←002

012

112

(Note 2)

CPUM4

←02

MISRG1

←12

MISRG1

←02

Reset released

State 1

Operation clock source:

f(XIN) (Note 1)

f(XIN) oscillation enabled

On-chip oscillator stop

State 2

Operation clock source:

f(XIN) (Note 1)

f(XIN) oscillation enabled

On-chip oscillator enabled

State 3

Operation clock source:

On-chip oscillator (Note 3)

f(XIN) oscillation enabled

On-chip oscillator enalbed

State 4

Operation clock source:

On-chip oscillator (Note 3)

f(XIN) oscillation stop

On-chip oscillator enalbed

Notes on switch of clock

(1) In operation clock source = f(XIN), the following can be

selected for the CPU clock division ratio.

q f(XIN)/2 (high-speed mode)

q f(XIN)/8 (middle-speed mode)

q f(XIN) (double-speed mode, only at a ceramic oscillation)

(2) Execute the state transition state 3 to state 2 or

state 3’ to state 2’ after stabilizing XIN oscillation.

(3) In operation clock source = on-chip oscillator, the middle-

speed mode is selected for the CPU clock division ratio.

(4) When the state transition state 2

→ state 3 → state 4

is performed, execute the NOP instruction as shown below

according to the division ratio of CPU clock.

• CPUM76

→ 102 (State 2 → state 3)

• NOP instruction

• CPUM4

→ 12 (State 3 → state 4)

Double-speed mode at on-chip oscillator: NOP ✕ 3

High-speed mode at on-chip oscillator: NOP ✕ 1

Middle-speed mode at on-chip oscillator: NOP ✕ 0

Reset state

CPUM76

←102

CPUM76

←002

012

112

(Note 2)

State 2’

Operation clock source:

f(XIN) (Note 1)

f(XIN) oscillation enabled

On-chip oscillator enabled

State 3’

Operation clock source:

On-chip oscillator (Note 3)

f(XIN) oscillation enabled

On-chip oscillator enalbed

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