7540 datasheet(324/366 Pages) RENESAS

324 / 366 page

3-102

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

APPENDIX

7540 Group

3.5 List of registers

Fig. 3.5.9 Structure of Serial I/O1 control register

Serial I/O1 control register

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Serial I/O1 control register (SIO1CON) [Address : 1A 16]

0 : f(XIN)

1 : f(XIN)/4

BRG count source

selection bit (CSS)

0 : Transmit disabled

1 : Transmit enabled

0 : Receive disabled

1 : Receive enabled

Transmit interrupt

source selection bit (TIC)

Transmit enable bit (TE)

Receive enable bit (RE)

Serial I/O1 enable bit

(SIOE)

0 : Interrupt when transmit buffer

has emptied

1 : Interrupt when transmit shift

operation is completed

0: Serial I/O1 disabled

1: Serial I/O1 enabled

Serial I/O1 synchronous clock

selection bit (SCS)

When clock synchronous serial I/O

is selected;

0: BRG output divided by 4

1: External clock input

When UART is selected;

0: BRG output divided by 16

1: External clock input divided by 16

SRDY1 output enable bit

(SRDY)

0: P13 pin

1: SRDY1 output pin

Serial I/O1 mode selection bit

(SIOM)

0: Clock asynchronous (UART)

serial I/O

1: Clock synchronous serial I/O

Fig. 3.5.10 Structure of UART control register

b7b6b5b4b3 b2b1b0

Function

At reset

Name

UART control register (UARTCON) [Address : 1B16]

Nothing is allocated for these bits. These are write disabled bits.

When these bits are read out, the values are “1”.

UART control register

Character length

selection bit (CHAS)

Parity enable bit

(PARE)

Stop bit length selection

bit (STPS)

Parity selection bit

(PARS)

In output mode

0 : CMOS output

1 : N-channel open-drain

output

0 : 8 bits

1 : 7 bits

0 : Parity checking disabled

1 : Parity checking enabled

0 : 1 stop bit

1 : 2 stop bits

0 : Even parity

1 : Odd parity

P11/TxD P-channel

output disable bit

(POFF)

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