7220 datasheet(197/303 Pages) RENESAS

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APPLICATION

5.4 Example of I2C-BUS interface control (M37221Mx-XXXSP/FP)

7220 Group User’s Manual

5-24

(2)

Read processing routine

Fig. 5.4.5 Flowchart of read processing routine

Slave address

(W) “A016”

Sub-address

Data

Slave address

(R) “A116”

Read start

S1 (address 00D9 16)

←“001000002”

(A)

←Slave address (R) “A1 16”

(A)

←Slave address (W) “A0 16”

Transmit the START condition, slave

address (W) , and sub-address.

Immediately before

the last receive byte?

Input start

(Set dummy data to

generate clock.)

End of reception of

the last receive byte

Preparation for judging of timeout.

Store recive data to internal RAM

Data output

Timeout ? (See note 2)

End

PIN (bit 4 at address 00D9 16)

≠“1”?

Data output

Yes

Waiting receive end

Yes (end)

No (not end)

Yes

Set to receive mode

Set ACK return mode.

After data is received, no

acknowledge bits are

generated, but the STOP

condition is sent by the

master, completing this

read operation.

Set to non-ACK return mode.

Initialization

S2 (address 00DB 16)

S1D (address 00DA 16)

S1 (address 00D9 16)

IICE (bit6 at address 00FE 16)

←“110001012”

←“010010002”

←“0”

←“000100002”

Disable multi-master I 2C-BUS interface.

Setting for outputting the START condition

in data output processing routine.

TRX (bit 6 at address 00D9 16)

ACK BIT (bit 6 at address 00DB 16)

←“0”

ACK BIT (bit 6 at address 00DB 16)

←“1”

S0 (address 00D7 16)

←“FF16”

S1 (address 00F8 16)

←“1”

←“110000002”

←“110100002”

←“0”

Transmit the STOP condition.

Note 1: Be sure to set between S1

and S1 within 10 machine cycles.

Transmit the RESTART condtion and

slave address (R).

Note 2: The timeout count is performed by software with interrupts, such as timers. Accordingly, if receive

2C-BUS access is stopped by timeout, the obtained data is incorrect data.

S0:

S1:

S2:

S1D:

IICE:

BB:

TRX:

ACK BIT:

PIN:

RS:

Accumulator

I2C data shift register

I2C status register

I2C clock control register

I2C control register

Multi-master I 2C interface

interrupt enable bit

Bus busy flag

Communication mode

specification bit

ACK bit

I2C-BUS interface interrupt

request bit

Restart condition

Within 10

machine

cycles

operation does not complete within a certain time, I C-BUS access is stopped by outputting STOP

operation is not completed due to various influences, the loop continues. Therefore, if receive

condition. If I

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