4513 datasheet(150/210 Pages) RENESAS

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APPLICATION

2.4 Serial I/O

2-47

4513/4514 Group User’s Manual

Fig. 2.4.6 Slave serial I/O example

Disable Interrupts

Serial I/O interrupt is temporarily disabled.

Interrupt enable flag INTE

Interrupt control register V2

“0”

All interrupts disabled (DI instruction)

Serial I/O interrupt occurrence disabled

(TV2A instruction)

Set Serial I/O

Serial I/O mode register J1

! 1

Exernal clock selected (TJ1A instruction)

Serial I/O port selected

g0 h

Clear Interrupt Request

Serial I/O interrupt activated condition is cleared.

Serial I/O transmit/receive

completion flag SIOF

“0”

Serial I/O interrupt activated condition cleared

(SNZSI instruction)

Note when the interrupt request is cleared

When is executed, considering the skip of the next instruction according to the

SIOF flag, insert the NOP instruction after the SNZSI instruction.

When interrupt is

not used

When interrupt is used

Set Interrupt

Interrupts except serial I/O is enabled

(EI instruction)

Set Interrupt

Serial I/O interrupt temporarily disabled is enabled.

1 !!!

Interrupt control register V2

Serial I/O interrupt occurrence

enabled (TV2A instruction)

Interrupt enable flag INTE

“1”

All interrupts enabled

(EI instruction)

Set When Transmit/Receive Operation Start Enabled

Serial transfer start state (SST instruction)

System enters to control signal transmission enabled state (“L” level)

However, SCK pin initial level = “H” level

Start Serial I/O Operation

Serial transfer starts by clock of master side

Check Serial I/O Interrupt Request

SIOF flag is checked (SNZSI instruction).

Serial I/O Interrupt Occur

Receive Data Processing

System enters to control signal transmission disabled state (“H” level)

Data processing received by serial transfer is executed.

→ register A, register B (TABSI instruction)

When serial communication is executed, to are repeated.

“!”: it can be “0” or “1.”

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