4513 datasheet(165/210 Pages) RENESAS

165 / 210 page

APPLICATION

2-62

4513/4514 Group User’s Manual

2.9 RAM back-up

(4)

Interrupt control register I2

The interrupt valid waveform for INT1 pin/return level selection bit is assigned to bit 2, the INT1 pin

edge detection circuit control bit is assigned to bit 1, and the INT1 pin timer 1 control enable bit is

assigned to bit 1.

Set the contents of this register through register A with the TI2A instruction.

In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A.

Table 2.9.7 shows the interrupt control register I2.

Table 2.9.7 Interrupt control register I2

Interrupt control register I2

at reset : 00002

at RAM back-up : state retained

R/W

This bit has no function, but read/write is enabled.

Falling waveform (“L” level of INT1 pin is recognized

with the SNZI1 instruction)/“L” level

Rising waveform (“H” level of INT1 pin is recognized

with the SNZI1 instruction)/“H” level

One-sided edge detected

Both edges detected

Disabled

Enabled

Not used

Interrupt valid waveform for INT1

pin/return level selection bit

(Note 2)

INT1 pin edge detection circuit

control bit

INT1 pin

timer 3 control enable bit

I23

I22

I21

I20

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set.

Accordingly, clear EXF1 flag with the SNZ1 instruction.

2.9.3 Notes on use

(1)

Key-on wakeup function

After setting ports (P1 specified with register PU0 and P0) which key-on wakeup function is valid to

“H,” execute the POF instruction.

“L” level is input to the falling edge detection circuit even if one of ports which key-on wakeup

function is valid is in the “L” level state, and the edge is not detected.

(2)

POF instruction

Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM

back-up state.

Note that system cannot enter the RAM back-up state when executing only the POF instruction.

Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.

(3)

Return from RAM back-up

After system returns from RAM back-up, set the undefined registers and flags.

Especially, be sure to set data pointer (registers Z, X, Y).

4513 Datasheet(PDF) 165 Page - Renesas Technology Corp

4513 Datasheet(HTML) 165 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL