H83069RF datasheet(183/1003 Pages) RENESAS

183 / 1003 page

Rev. 5.0, 09/04, page 161 of 978

The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh

cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the

WAIT pin.

Tc1

Tc2

(

UCAS /LCAS)

PB4/PB5

RD(WE)

CSn(RAS)

D15 to D0

RD(WE)

D15 to D0

(

UCAS /LCAS)

PB4/PB5

A23 to A0

Trw

Write access

Read access

Read data

Write data

Note: n = 2 to 5

Row

Column

High level

Figure 6.20 Example of Wait State Insertion Timing (CSEL = 0)

6.5.9

Byte Access Control and

CAS

CAS Output Pin

When an access is made to DRAM space designated as a 16-bit-access area in ABWCR, column

address strobes (

UCAS and LCAS) corresponding to the upper and lower halves of the external

data bus are output. In the case of

× 16-bit organization DRAM, the 2-CAS type can be

connected.

Either PB4 and PB5, or

HWR and LWR, can be used as the UCAS and LCAS output pins, the

selection being made with the CSEL bit in DRCRB. Table 6.8 shows the CSEL bit settings and

corresponding output pin selections.

H83069RF Datasheet(PDF) 183 Page - Renesas Technology Corp

H83069RF Datasheet(HTML) 183 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL