H83069RF datasheet(186/1003 Pages) RENESAS

186 / 1003 page

Rev. 5.0, 09/04, page 164 of 978

Table 6.9

Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and

Row Address Compared in Burst Access

DRCRB

ABWCR

Operating Mode

MXC1

MXC0

ABWn

Bus Width

Compared Row Address

Modes 1 and 2

16 bits

A19 to A9

(1-Mbyte)

8 bits

A19 to A8

16 bits

A19 to A10

8 bits

A19 to A9

16 bits

A19 to A11

8 bits

A19 to A10

—

Illegal setting

Modes 3, 4, and 5

16 bits

A23 to A9

(16-Mbyte)

8 bits

A23 to A8

16 bits

A23 to A10

8 bits

A23 to A9

16 bits

A23 to A11

8 bits

A23 to A10

—

Illegal setting

Note:

n = 2 to 5

RAS Down Mode and RAS Up Mode: With DRAM provided with fast page mode, as long as

accesses are to the same row address, burst operation can be continued without interruption even

if accesses are not consecutive by holding the

RAS signal low.

• RAS Down Mode

To select RAS down mode, set the BE and RDM bits to 1 in DRCRA. If access to DRAM

space is interrupted and another space is accessed, the

RAS signal is held low during the

access to the other space, and burst access is performed if the row address of the next DRAM

space access is the same as the row address of the previous DRAM space access. Figure 6.23

shows an example of the timing in RAS down mode.

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