OUTPUT VOLTAGE LIMITATIONS

(

)

(

)

(

)

Omax

IN min

O max

DSon max

D

O max

L

D

V

= 0.91 ×

V

I

× R

+ V

I

× R

V

-

-

-

(31)

(

)

(

)

(

)

Omin

IN max

Omin

D

O min

L

D

V

= 0.089

V

I

Rin

+ V

I

R

V

´

-

´

-

´

-

(32)

POWER DISSIPATION ESTIMATE

TPS54331

Due to the internal design of the TPS54331, there are both upper and lower output voltage limits for any given

input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 91%

and is given by Equation 31:

Where:

The equation assumes maximum on resistance for the internal high-side FET.

The lower limit is constrained by the minimum controllable on time which may be as high as 130 ns. The

approximate minimum output voltage for a given input voltage and minimum load current is given by Equation 32:

Where:

This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of

operating frequency set point. Any design operating near the operational limits of the device should be carefully

checked to assure proper functionality.

The following formulas show how to estimate the device power dissipation under continuous conduction mode

operations. They should not be used if the device is working in the discontinuous conduction mode (DCM) or

The device power dissipation includes:

Where:

IOUT is the output current (A).

Rds(on) is the on-resistance of the high-side MOSFET (

Ω).

VOUT is the output voltage (V).

VIN is the input voltage (V).

Fsw is the switching frequency (Hz).

So

Ptot = Pcon + Psw + Pgc + Pq

16

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