CE5037

Data Sheet

7

Intel Corporation

The output of the phase detector feeds a charge pump which combined with an external loop filter integrates the

current pulses to control the varactor voltage. The charge pump current is automatically varied by the VCO control

logic to compensate for VCO gain variations that are dependent on selected sub band. The varactor control voltage

is externally coupled to the oscillator section through the input pin Vvar.

1.4

formats.

either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into

format.

The CE5037 contains 16 control registers. These registers are read/write registers. These registers are addressed

access sequential write and read as shown below.

Random Access Single Write

Random Access Sequential Write

Stop

Random Access Single Read

Random Access Sequential Read

W

Write bit

A

Acknowledge Bit

N

Not Acknowledge

interface.

Stop

Start

Device

Address

W A

Register

Address

N

A

Register

Data

N

A

Stop

Stop

Start

Device

Address

W A

Register

Address

N

A

Register

Data

N

A

Register

Data

N+1

...

Register

Data

N+M

A

Stop

Stop

Start

Device

Address

W A

Register

Address

N

A

Start

Device

Address

R A

Register

Data

N

N Stop

Stop

Start

Device

Address

W A

Register

Address

N

A

Start

Device

Address

R A

Register

Data

N

A

...

Register

Data

N+M

N Stop