CE5037

Data Sheet

9

Intel Corporation

2.1

PLL Registers

There are four registers that control the PLL:

The PLF bit is the PLL lock detect circuit output. The PLF bit is set after 64 consecutive comparison cycles in lock.

A chip-wide reset initializes the lock detect output to 0.

programmable to integer values within the range of 240 to 32767.

Note that when the LO Divider divide value is to be changed, the new value is not actually presented to the LO

programmed (in any order) before the LO divider is updated even if the only data change is in one of the registers.

The C[1:0] bits set the programmed charge pump current

.

The charge pump current is automatically increased to the next setting dependent on the VCO sub band that has

been selected by the VCO tuning algorithm. This is to compensate for changes in VCO gain and so provide

consistent PLL performance across all sub bands. Programming the highest charge pump value will not allow the

value to be incremented, therefore this value should not be programmed.

The value read back for the charge pump current is the actual value in use for the selected sub band.

Bit Field

Name

Default

Type

Description

7

PLF

-

R

PLL Lock Flag

6:0

0

R/W

MSB bits of LO Divider register

Table 3 - Register 0

Bit Field

Name

Default

Type

Description

7:0

0

R/W

LSB bits of LO Divider register

Table 4 - Register 1

Bit Field

Name

Default

Type

Description

7:6

-

0

R/W

Test modes

5:4

C[1:0]

0

R/W

Charge pump current

3:0

R[3:0]

0

R/W

Reference divider ratio

Table 5 - Register 2

C[1]

C[0]

Typ

Units

0

0

400

uA

0

1

550

uA

1

0

750

uA

1

1

1000

uA

Table 6 - Charge Pump Currents