AD5590BBCZ datasheet(32/44 Pages) AD

32 / 44 page

AD5590

Rev. 0 | Page 32 of 44

The bias generator of the selected DAC(s), output amplifier,

resistor string, and other associated linear circuitry are shut

down when the power-down mode is activated. The internal

reference is powered down only when all channels are powered

down. However, the contents of the DAC register are unaffected

when in power-down. The time to exit power-down is typically

4 μs for DACVDD = 5 V.

Any combination of DACs can be powered up by setting PD1

and PD0 to 0 (normal operation). The output powers up to the

value in the input register (LDAC low) or to the value in the

DAC register before powering down (LDAC high).

DAC Clear Code Register

The DAC blocks have a hardware CLR pin that is an asynchron-

ous clear input for all 16 DACs. The CLR input is falling edge

sensitive. Bringing the CLR line low clears the contents of the

input register and the DAC registers to the data contained in

the user-configurable CLR register and sets the analog outputs

accordingly. This function can be used in system calibration to

load zero scale, midscale, or full scale to all channels together.

These clear code values are user-programmable by setting Bit DB1

and Bit DB0 in the CLR control register (see Table 17). The

default setting clears the outputs to 0 V. Command 0101 is

reserved for loading the clear code register (see Table 11).

The DAC exits clear code mode on the 32nd falling edge of

the next write to the DAC. If CLR is activated during a write

sequence, the write is aborted.

The CLR pulse activation time—the falling edge of CLR to

when the output starts to change—is typically 280 ns. However,

if outside the DAC linear region, it typically takes 520 ns after

executing CLR for the output to start changing.

See Table 18 for contents of the input shift register during the

loading clear code register operation.

Table 15. DAC Power-Down Modes of Operation

DB9

DB8

Operating Mode

Normal operation

Power-down modes:

1 kΩ to GND

100 kΩ to GND

Three-state

Table 16. DAC 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function

MSB

LSB

DB31 to

DB28

DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20

DB19

to DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

PD1

PD0

DAC

Don’t care

Command bits (C3 to C0)

Address bits (A3 to A0)—

don’t care

Don’t

care

Power-down

mode

Power-down/power-up channel selection—set bit to 1

to select

Table 17. DAC Clear Code Register

Clear Code Register

DB1

DB0

CR1

CR0

Clears to Code

0x0000

0x0800

0x0FFF

No operation

Table 18. DAC 32-Bit Input Shift Register Contents for Clear Code Function

MSB

LSB

DB31 to DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19 to DB2

DB1

DB0

CR1

CR0

Don’t care

Command bits (C3 to C0)

Address bits (A3 to A0)—don’t care

Don’t care

Clear code register

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