AD5590BBCZ datasheet(35/44 Pages) AD

35 / 44 page

AD5590

Rev. 0 | Page 35 of 44

AutoShutdown (PM1 = 0, PM0 = 1)

In this mode, the ADC automatically enters shutdown at the

end of each conversion when the ADC control register is updated.

When the ADC is in shutdown, the track-and-hold is in hold

mode. Figure 66 shows the general diagram of the operation of

the ADC in this mode. In shutdown mode, all internal circuitry

on the ADC is powered down. The ADC retains information in

the ADC control register during shutdown. The ADC remains

in shutdown until the next ASYNC falling edge it receives. On

this ASYNC falling edge, the track-and-hold that was in hold

while the ADC was in shutdown returns to track. Wake-up time

from autoshutdown is 1 μs, and the user should ensure that 1 μs

has elapsed before attempting a valid conversion. When running

the ADC with a 20 MHz clock, one dummy cycle of 16 × ASCLKs

should be sufficient to ensure that the ADC is fully powered up.

During this dummy cycle, the contents of the ADC control

should be 0 on the ADIN line. This dummy cycle effectively

halves the throughput rate of the ADC, with every other

conversion result being valid. In this mode, the power

consumption of the ADC is greatly reduced with the ADC

entering shutdown at the end of each conversion. When the

ADC control register is programmed to move into

autoshutdown, it does so at the end of the conversion. The user

can move the ADC in and out of the low power state by

controlling the ASYNC signal.

Autostandby (PM1 = PM0 = 0)

In this mode, the ADC automatically enters standby mode at

the end of each conversion when the ADC control register is

updated. Figure 67 shows the general diagram of the operation

of the ADC in this mode. When the ADC is in standby, portions

of the ADC are powered down, but the on-chip bias generator

remains powered up. The ADC retains information in the ADC

control register during standby. The ADC remains in standby

until it receives the next ASYNC falling edge. On this ASYNC

falling edge, the track and hold that was in hold while the ADC

was in standby returns to track. Wake-up time from standby is 1

μs; the user should ensure that 1 μs has elapsed before attempting a

valid conversion on the ADC in this mode. When running the

ADC with a 20 MHz clock, one dummy cycle of 16 × ASCLKs

should be sufficient to ensure the ADC is fully powered up.

During this dummy cycle, the contents of the ADC control register

should remain unchanged; therefore, the write bit should be set

to 0 on the ADIN line. This dummy cycle effectively halves the

throughput rate of the ADC with every other conversion result

being valid. In this mode, the power consumption of the ADC

is greatly reduced with the ADC entering standby at the end of

each conversion. When the ADC control register is programmed

to move into autostandby, it does so at the end of the conver-

sion. The user can move the ADC in and out of the low power

state by controlling the ASYNC signal.

ASCLK

116

ADOUT

ADIN

ASYNC

DUMMY CONVERSION

CONTROL REGISTER IS LOADED ON THE

FIRST 12 CLOCKS, PM1 = 0, PM0 = 1

CONTROL REGISTER CONTENTS SHOULD

NOT CHANGE, WRITE BIT = 0

PART ENTERS

SHUTDOWN ON CS

RISING EDGE AS

PM1 = 0, PM0 = 1

PART IS FULLY

POWERED UP

TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 1

IN CONTROL REGISTER OR SET WRITE BIT = 0

CHANNEL IDENTIFIER BITS + CONVERSION RESU

DATA IN TO CONTROL/SHADOW REGISTER

CHANNEL IDENTIFIER BITS + CONVERSION RESU

DATA IN TO CONTROL/SHADOW REGISTER

INVALID DATA

PART ENTERS

SHUTDOWN ON ASYNC

RISING EDGE AS

PM1 = 0, PM0 = 1

PART BEGINS

TO POWER

UP ON ASYNC

FALLING EDGE

Figure 66. Autoshutdown Mode Operation

ASCLK

ADOUT

ADIN

ASYNC

DUMMY CONVERSION

CONTROL REGISTER IS LOADED ON THE

FIRST 12 CLOCKS, PM1 = 0, PM0 = 0

CONTROL REGISTER CONTENTS SHOULD

REMAIN UNCHANGED, WRITE BIT = 0

PART IS FULLY

POWERED UP

TO KEEP PART IN THIS MODE, LOAD PM1 = 0,

PM0 = 0 IN CONTROL REGISTER

PART ENTERS

STANDBY ON ASYNC

RISING EDGE AS

PM1 = 0, PM0 = 0

PART ENTERS

STANDBY ON ASYNC

RISING EDGE AS

PM1 = 0, PM0 = 0

PART BEGINS

TO POWER

UP ON ASYNC

FALLING EDGE

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

INVALID DATA

DATA IN TO CONTROL/SHADOW REGISTER

Figure 67. Autostandby Mode Operation

AD5590BBCZ Datasheet(PDF) 35 Page - Analog Devices

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