AD5590BBCZ datasheet(10/44 Pages) AD

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AD5590

Rev. 0 | Page 10 of 44

DAC Timing Characteristics

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4.

DACVDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.

Table 6.

Parameter1

Limit at TMIN, TMAX; DACVDD = 2.7 V to 5.5 V

Unit

Conditions/Comments

t12

ns min

DSCLK cycle time

ns min

DSCLK high time

ns min

DSCLK low time

ns min

DSYNC to DSCLK falling edge setup time

ns min

Data setup time

ns min

Data hold time

ns min

DSCLK falling edge to DSYNC rising edge

ns min

Minimum DSYNC high time

ns min

DSYNC rising edge to DSCLK fall ignore

t10

ns min

DSCLK falling edge to DSYNC fall ignore

t11

ns min

LDAC pulse width low

t12

ns min

DSCLK falling edge to LDAC rising edge

t13

ns min

CLR pulse width low

t14

ns min

DSCLK falling edge to LDAC falling edge

t15

300

ns typ

CLR pulse activation time

1 Sample tested at 25°C to ensure compliance.

2 Maximum DSCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.

DSCLK

DSYNCx

DDIN

DB31

t10

t11

t12

LDAC1

LDAC2

t14

1ASYNCHRONOUS LDAC UPDATE MODE.

2SYNCHRONOUS LDAC UPDATE MODE.

CLR

t13

t15

VOUTx

DB0

Figure 4. DAC Timing Characteristics

AD5590BBCZ Datasheet(PDF) 10 Page - Analog Devices

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