AD5590BBCZ datasheet(30/44 Pages) AD

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AD5590

Rev. 0 | Page 30 of 44

SERIAL INTERFACE

The AD5590 contains independent serial interfaces for the

ADC and DAC sections. The ADC uses the ASYNC, ASCLK,

ADIN, and ADOUT pins. The VDRIVE pin allows the user to

determine the output voltage of logic high signals. The DAC

uses DSCLK, DDIN, DSYNC1, DSYNC2, LDAC, and CLR.

The 16 analog input channels use the ADC interface. The 16

output channels use the DAC interface. The 16 output channels

are divided into two groups of eight channels, which can be

controlled independently. Each group has its own set of control

registers. When addressing the DAC control registers, the serial

data should be framed by DSYNC1 to access the control registers

for DAC0 to DAC7 and framed by DSYNC2 to access the control

registers for DAC8 to DAC15.

The interfaces are compatible with SPI®, QSPI™, MICROWIRE™,

and most DSPs.

ACCESSING THE DAC BLOCK

Figure 4 shows a timing diagram of a typical write sequence to

the DAC block. The write sequence begins by bringing one or

both of the DSYNC lines low. If DSYNC1 is brought low, the

data is written to the DAC block containing DAC0 to DAC7.

If DSYNC2 is brought low, the data is written to the DAC block

containing DAC8 to DAC15. If both DSYNC1 and DSYNC2 are

brought low, the data is written into both blocks simultaneously.

shows how the serial interface is arranged.

Figure 60

DDIN

DSYNC1

DSCLK

CLR

LDAC

GROUP 1

CONTROL

REGISTERS

DSYNC2

VOUT0

DAC 0

VOUT7

DAC 7

GROUP 2

CONTROL

REGISTERS

VOUT8

DAC 8

VOUT15

DAC 15

Figure 60. DAC Serial Interface Configuration

Data from the DDIN line is clocked into the 32-bit shift register

on the falling edge of DSCLK. The serial clock frequency can be

as high as 50 MHz, making the AD5590 compatible with high

speed DSPs. On the 32nd falling clock edge, the last data bit is

clocked in and the programmed function is executed, that is,

a change in DAC register contents and/or a change in the mode

of operation. At this stage, the DSYNCx line can be kept low

or be brought high. In either case, it must be brought high for

a minimum of 15 ns before the next write sequence so that a

falling edge of DSYNCx can initiate the next write sequence.

DAC Input Shift Register

The input shift register is 32 bits wide (see Figure 61). The first

four bits are don’t cares. The next four bits are the command

bits, C3 to C0 (see Table 11), followed by the 4-bit DAC address,

A3 to A0 (see Table 12), and finally the 12-bit data-word. The

data-word comprises the 12-bit input code followed by eight

don’t care bits. These data bits are transferred to the DAC

Table 11. DAC Command Definitions

Command

Description

Write to Input Register n

Update DAC Register n

Write to Input Register n, update all

(Software LDAC)

Write to and update DAC Channel n

Power down/power up DAC

Load clear code register

Load LDAC register

Reset (power-on reset)

Set up internal REF register

Reserved

…

Reserved

Table 12. DAC Address Commands

Address (n)

Selected DAC Channel

DSYNC1 Low

DSYNC2 Low

DAC0

DAC8

DAC1

DAC9

DAC2

DAC10

DAC3

DAC11

DAC4

DAC12

DAC5

DAC13

DAC6

DAC14

DAC7

DAC15

DAC0 to DAC7

DAC8 to DAC15

ADDRESS BITS

COMMAND BITS

A0 D11 D10 D9

DB31 (MSB)

DB0 (LSB)

DATA BITS

Figure 61. DAC Input Register Contents

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