AD5722/AD5732/AD5752

Rev. 0 | Page 26 of 32

CONTROL REGISTER

The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the

control function selected. The control register options are shown in Table 23 and Table 24.

Table 23. Programming the Control Register

MSB

LSB

R/W

Zero

REG2

REG1

REG0

A2

A1

A0

DB15 to DB4

DB3

DB2

DB1

DB0

0

0

0

1

1

0

0

0

NOP, data = don’t care

0

0

0

1

1

0

0

1

Don’t care

TSD enable

Clamp enable

CLR select

SDO disable

0

0

0

1

1

1

0

0

Clear, data = don’t care

0

0

0

1

1

1

0

1

Load, data = don’t care

Table 24. Explanation of Control Register Options

Option

Description

NOP

No operation instruction used in readback operations.

Clear

Addressing this function sets the DAC registers to the clear code and updates the outputs.

Load

Addressing this function updates the DAC registers and, consequently, the DAC outputs.

SDO Disable

Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).

CLR Select

See Table 25 for a description of the CLR select operation.

Clamp Enable

Set by the user to enable the current-limit clamp. The channel does not power down upon detection of an overcurrent; the

current is clamped at 20 mA (default).

Cleared by the user to disable the current-limit clamp. The channel powers down upon detection of an overcurrent.

TSD Enable

Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown feature (default).

Table 25. CLR Select Options

Output CLR Value

CLR Select Setting

Unipolar Output Range

Bipolar Output Range

0

0 V

0 V

1

Midscale

Negative full-scale

POWER CONTROL REGISTER

The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the

power and thermal status of the AD5722/AD5732/AD5752. The power control register options are shown in Table 26 and Table 27.

Table 26. Programming the Power Control Register

MSB

LSB

R/W

Zero

REG2

REG1

REG0

A2

A1

A0

DB15 to

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

1

0

0

0

0

X

0

X

X

TSD

X

X

X

Table 27. Power Control Register Functions

Option

Description

PU

A

DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down

mode (default). If the clamp enable bit of the control register is cleared, DAC A powers down automatically upon detection of an

overcurrent and PU

PU

B

DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down

mode (default). If the clamp enable bit of the control register is cleared, DAC A powers down automatically upon detection of an

overcurrent and PU

TSD

Thermal shutdown alert (read-only bit). In the event of an overtemperature situation, both DACs are powered down and this bit is set.

OC

A

DAC A overcurrent alert (read-only bit). In the event of an overcurrent situation on DAC A, this bit is set.

OC

B

DAC B overcurrent alert (read-only bit). In the event of an overcurrent situation on DAC B, this bit is set.