AD5722R/AD5732R/AD5752R

Preliminary Technical Data

Rev. PrC | Page 12 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

AD5722R/

AD5732R/

AD5752R

CLR

LDAC

NC

NC

SYNC

NC

BIN/2sCOMP

GND

SDO

REFIN/REFOUT

SIG_GND

SCLK

SDIN

NC

NC = NO CONNECT

NC

SIG_GND

DAC_GND

DAC_GND

NC

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

Negative Analog Supply Pin. Voltage ranges from –4.5 V to –16.5 V. This pin can be connected to 0 V if output

ranges are unipolar.

2, 4, 6, 12,

13, 22

NC

Do not connect to these pins.

3

Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.

5

BIN/2sCOMP

complement. (For unipolar output ranges, coding is always straight binary).

7

SYNC

Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is

transferred on the falling edge of SCLK.

8

SCLK

Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock

speeds up to 30 MHz.

9

SDIN

Serial Data Input. Data must be valid on the falling edge of SCLK.

10

LDAC

Load DAC, Logic Input. This is used to update the DAC registers and consequently, the analog output. When

tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high

during the write cycle, the DAC input register is updated, but the output update is held off until the falling

edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC.

The LDAC pin should not be left unconnected.

11

Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or mid-scale code (user-selectable).

14

Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.

15

GND

Ground Reference Pin.

16

SDO

Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is

clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.

17

REFIN/REFOUT

External Reference Voltage Input and Internal Reference Voltage Output. Reference input range is 2 V to 3 V.

REFIN = 2.5 V for specified performance. REFOUT = 2.5 V ± 2 mV.

18, 19

DAC_GND

Ground reference pins for the four digital-to-analog converters.

20, 21

SIG_GND

Ground reference pins for the four output amplifiers.

23

Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.

24

Positive Analog Supply Pin. Voltage ranges from 4.5 V to 16.5 V.

Exposed

Paddle

Negative Analog Supply connection. Voltage ranges from -4.5V to -16.5V. This paddle can be connected to 0V

if output ranges are unipolar.