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AD5752R Datasheet(PDF) 27 Page - Analog Devices |
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AD5752R Datasheet(HTML) 27 Page - Analog Devices |
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27 / 32 page ![]() Preliminary Technical Data AD5722R/AD5732R/AD5752R Rev. PrC | Page 27 of 32 INPUT REGISTER The input register is 24 bits wide and consists of a read/write bit, a reserved bit, three register select bits, three DAC address bits, and 12- /14-/16 data bits. The register data is clocked in MSB first on the SDIN pin. Table 18 shows the register format while Table 19 describes the function of each bit in the register. All registers are read/write registers. Table 18. Input Register Format MSB LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB0 R/W 0 REG2 REG1 REG0 A2 A1 A0 DATA Table 19. Input Register Bit Functions Bit Mnemonic Description R/W Indicates a read from or a write to the addressed register. REG2, REG1, REG0 Used in association with the address bits to determine if a write operation is to the data register, output range select register, power control register, or control register. REG2 REG1 REG0 Function 0 0 0 Data Register 0 0 1 Output Range Select Register 0 1 0 Power Control Register 0 1 1 Control Register A2, A1, A0 These bits are used to decode the DAC channels. A2 A1 A0 Channel Address 0 0 0 DAC A 0 1 0 DAC B 1 0 0 Both DACs DB15 to DB0 Data bits. DATA REGISTER The data register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel where the data transfer is to take place (see Table 19). The data bits are in positions DB15 to DB0 for the AD5752R (see Table 20), DB15 to DB2 for the AD5732R (see Table 21), and DB15 to DB4 for the AD5722R (see Table 22). Table 20. Programming the AD5752R Data Register MSB LSB REG2 REG1 REG0 A2 A1 A0 DB15 to DB0 0 0 0 DAC Address 16-Bit DAC Data Table 21. Programming the AD5732R Data Register MSB LSB REG2 REG1 REG0 A2 A1 A0 DB15 to DB2 DB1 DB0 0 0 0 DAC Address 14-Bit DAC Data X X Table 22. Programming the AD5722R Data Register MSB LSB REG2 REG1 REG0 A2 A1 A0 DB15 to DB4 DB3 DB2 DB1 DB0 0 0 0 DAC Address 12-Bit DAC Data X X X X |
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