Preliminary Technical Data

AD5722R/AD5732R/AD5752R

Rev. PrC | Page 29 of 32

POWER CONTROL REGISTER

The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power

and thermal status of the AD5722R/AD5732R/AD5752R. The power control register options are shown in Table 28 and Table 29.

Table 28. Power Control Register Format

MSB

LSB

REG2

REG1

REG0

A2

A1

A0

DB15 to DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

0

0

0

Don’t Care

X

X

0

TSD

X

X

Table 29. Explanation of Status Register Options

Option

Description

DAC A Power-Up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down

mode (default). If the CLAMP ENABLE bit of the control register is cleared, DAC A will power down autimatically on detection of

DAC B Power-Up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down

mode (default). If the CLAMP ENABLE bit of the control register is cleared, DAC B will power down autimatically on detection of an

Reference Power-Up. When set, this bit places the internal reference in normal operating mode. When cleared, this bit places the

internal reference in power-down mode (default).

TSD

Thermal Shutdown Alert. Read-Only Bit. In the event of an overtemperature situation, this bit is set.

DAC A Overcurrent Alert. Read-Only Bit. In the event of an overcurrent situation on DAC A, this bit is set.

DAC B Overcurrent Alert. Read-Only Bit. In the event of an overcurrent situation on DAC B, this bit is set.