AD9714 datasheet(34/48 Pages) AD

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AD9714/AD9715/AD9716/AD9717

Rev. 0 | Page 34 of 48

SPI REGISTER DESCRIPTIONS

Reading these registers returns previously written values for all defined register bits, unless otherwise noted.

Table 14.

Address

Bit

Name

Function

SPI Control

0x00

LSBFIRST

0: MSB first, per SPI standard

1: LSB first, per SPI standard

Note that the user must always change the LSB/MSB order in single-byte instructions

to avoid erratic behavior due to bit order errors

RESET

Execute software reset of SPI and controllers, reload default register values except

1: Set software reset; write 0 on the next (or any following) cycle to release the reset

LNGINS

0: The SPI instruction word utilizes a 5-bit address

1: The SPI instruction word utilizes a 13-bit address

Power Down

0x01

LDOOFF

1: turn core LDO voltage regulator off

LDOSTAT

0: Indicates core LDO voltage regulator is off

1: Indicates core LDO voltage regulator is on

PWRDN

1: Powers down all analog and digital circuitry except for SPI logic

Q DACOFF

1: Turns off Q DAC output current

I DACOFF

1: Turns off I DAC output current

QCLKOFF

1: Turns off Q DAC clock

ICLKOFF

1: Turns off I DAC clock

EXTREF

1: Powers down internal voltage reference (external reference required)

Data Control

0x02

TWOS

0: Unsigned binary input data format

1: Twos complement input data format

IFIRST

0: Pairing of data—Q first of pair on data input pads

1: Pairing of data—I first of pair on data input pads (default)

IRISING

0: Q data latched on DCLKIO rising edge

1: I data latched on DCLKIO falling edge (default)

SIMULBIT

0: Allows simultaneous input and output enable on DCLKIO

1: Disallows simultaneous input and output enable on DCLKIO

DCI_EN

Controls the use of DCLKIO pad for data clock input

0: Data clock input disabled

1: Data clock input enabled (default)

DCOSGL

Controls the use of DCLKIO pad for data clock output

0: Data clock output disabled

1: Data clock output enabled; regular strength driver

DCODBL

Controls the use of DCLKIO pad for data clock output

0: DCOBL data clock output disabled

1: DCOBL data clock output enabled; paralleled with DCOSGL for 2× drive current

I DAC Gain

0x03

5:0

I DACGAIN[5:0]

DAC I fine gain adjustment; alters the full-scale current as shown in Figure 86

IRSET

0x04

IRSETEN

1: Enables the on-chip RSET value to be changed

5:0

IRSET[5:0]

Changes the value of the on-chip RSET resistor; this scales the full-scale current of the

DAC in ~0.25 dB steps (nonlinear); see Figure 85

000000: RSET = 8 kΩ

100000: RSET = 16 kΩ

111111: RSET = 32 kΩ

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