TS68230CFN10 datasheet(16/61 Pages) STMICROELECTRONICS

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ly effect on the PI/T caused by interrupt acknow-

ledge cycles is that the vector is placed on the data

bus. Specifically, no registers, data, status, or other

internal states of the PI/T are affected by the cycle.

Several conditions may be present when the PIACK

input is asserted to the PI/T. These conditions affect

the PI/T’s response and the termination of the bus

cycle. If the PI/T has no interrupt function selected,

or is not asserting PIRQ, the PI/T will make no res-

ponse to PIACK (DTACK will not be asserted). If the

PI/T is asserting PIRQ when PIACK is received, the

PI/T will output the contents of the port interrupt vec-

tor register and the prioritization bits. If the PIVR has

not been initialized, $0F will be read from this regis-

ter. These conditions are summarized in table 2.1.

The vector table entries for the PI/T appear as a

contiguous block of four vector numbers whose

common upper six bits are programmed in the PIVR.

The following table pairs each interrupt source with

the 2-bit value provided by the prioritization logic

when interrupt acknowledge is asserted (see 4.2.

Port Service Request Register (PSRR)).

H1 source - 00

H2 source - 01

H3 source - 10

H4 source - 11

2.2.2. AUTOVECTORED PORT INTERRUPTS.

Autovectored interrupts use only the PIRQ pin. The

operation of the PI/T with vectored and autovectored

interrupts is identical except that no vectors are sup-

plied and the PC6/PIACK pin can be used as a port

C pin.

2.2.3. DMA REQUEST OPERATION. The direct

memory access request (DMAREQ) pulse (when

enabled) is associated with output or input transfers

to keep the initial and final output latches full or initial

and final input latches empty, respectively. Figures

2.3 and 2.4 show all the possible paths in generating

DMA requests. See 4.2. Port Service Request Re-

gister (PSRR) for programming the operation of the

DMA request bit.

Table 2.1 : Response to Port Interrupt Acknowledge.

Conditions

PIRQ Negated O R Interrupt

Request Function not Selected

PIRQ Asserted

PIVR has not been initialized

since RESET.

No Response from PI/T.

No DTACK.

PI/T provides $0F, the Uninitialized

Vector*.

PIVR has been initialized

since RESET.

No Response from PI/T.

No DTACK.

PI/T provides PIVR contents with

prioritization bits.

* The uninitialized vector is the value returned from an interrupt vector register before it has been initialized.

* Synchronized means that the appropriate input signal (H1, H3, or CS) has been sampled by the PI/T on the appropriatre

edge of the

clock (rising edge for H1(H3) and falling edge for CS). Refer to 1.4 BUS INTERFACE OPERATION for the exception concer-

Figure 2.3 : DMAREQ Associated with Output

Transfers.

DMAREQ is generated on the bus side of the

TS68230 by the synchronized* chip select. If the

conditions of figures 2.3 or 2.4 are met, an assertion

of CS will cause DMAREQ to be asserted three PI/T

clocks (plus the delay time from the clock edge) after

CS is synchronized. DMAREQ remains asserted

three clock cycles (plus the delay time from the clock

edge) and is then negated.

DMAREQ pulses are associated with peripheral

transfers or are generated by the synchronized*

H1(H3) input. If the conditions of figures 2.3 or 2.4

are met, an assertion of the H1(H3) input will cause

DMAREQ to be asserted 2.5 PI/T clock cycles (plus

the delay time from clock edge) after H1(H3) is syn-

chronized. DMAREQ remains asserted three clock

cycles (plus the delay time from the clock edge) and

is then negated.

TS68230

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