P89LPC954 datasheet(32/69 Pages) NXP

32 / 69 page

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

32 of 69

NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

7.16 Reset

The P1.5/RST pin can function as either a digital input (P1.5), an active-LOW reset input

with an internal pull-up, a bidirectional reset input/output (open drain output with an

internal pull-up), or as push-pull reset output. These modes are selected by the RPE

(Reset Pin Enable) bit in UCFG1 and the RPE1 (Reset Pin Enable 1) bit in UCFG2.

Remark: During a power-up sequence, the RPE and RPE1 selection is overridden and

this pin always functions as a reset input. An external circuit connected to this pin

should not hold this pin LOW during a power-on sequence as this will keep the

device in reset. After power-up this pin will function as deﬁned by the RPE and RPE1

bits. Only a power-up reset will temporarily override the selection deﬁned by RPE and

RPE1 bits. Other sources of reset will not override the RPE and RPE1 bits.

Remark: During a power cycle, VDD must fall below VPOR before power is reapplied, in

order to ensure a power-on reset (see Table 11 “Static characteristics” on page 51).

Remark: When using an oscillator frequency above 12 MHz, the reset input function of

P1.5 must be enabled. An external circuit is required to hold the device in reset at

power-up until VDD has reached its speciﬁed level. When system power is removed VDD

will fall below the minimum speciﬁed operating voltage. When using an oscillator

frequency above 12 MHz, in some applications, an external brownout detect circuit may

be required to hold the device in reset when VDD falls below the minimum speciﬁed

operating voltage.

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user conﬁgured via UCFG1, UCGF2);

• Power-on detect;

• Brownout detect;

• Watchdog timer;

• Software reset;

• UART break character detect reset.

For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can read

this register to determine the most recent reset source. These ﬂag bits can be cleared in

software by writing a ‘0’ to the corresponding bit. More than one ﬂag bit may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

cleared.

• For any other reset, previously set ﬂag bits that have not been cleared will remain set.

Table 8.

Reset pin modes

P1.5/RST mode

RPE1 (UCFG2.0) RPE (UCFG1.6)

General purpose input

Reset input with pull-up

Bidirectional reset input/output (open drain with pull-up)

Reset output

P89LPC954 Datasheet(PDF) 32 Page - NXP Semiconductors

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