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P89LPC954 Datasheet(PDF) 53 Page - NXP Semiconductors |
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P89LPC954 Datasheet(HTML) 53 Page - NXP Semiconductors |
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53 / 69 page  P89LPC952_954_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 July 2008 53 of 69 NXP Semiconductors P89LPC952/954 8-bit microcontroller with 10-bit ADC 11. Dynamic characteristics Table 12. Dynamic characteristics (12 MHz) VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1][2] Symbol Parameter Conditions Variable clock fosc = 12 MHz Unit Min Max Min Max fosc(RC) internal RC oscillator frequency nominal f = 7.3728 MHz trimmed to ± 1 % at Tamb =25 °C; clock doubler option = OFF (default) 7.189 7.557 7.189 7.557 MHz nominal f = 14.7456 MHz; clock doubler option = ON, VDD = 2.7 V to 3.6 V 14.378 15.114 14.378 15.114 MHz fosc(WD) internal watchdog oscillator frequency 320 520 320 520 kHz fosc oscillator frequency 0 12 - - MHz Tcy(clk) clock cycle time see Figure 19 83 - - - ns fCLKLP low-power select clock frequency 0 8 - - MHz Glitch filter tgr glitch rejection time P1.5/RST pin - 50 - 50 ns any pin except P1.5/RST - 15 - 15 ns tsa signal acceptance time P1.5/RST pin 125 - 125 - ns any pin except P1.5/RST 50 - 50 - ns External clock tCHCX clock HIGH time see Figure 19 33 Tcy(clk) − tCLCX 33 - ns tCLCX clock LOW time see Figure 19 33 Tcy(clk) − tCHCX 33 - ns tCLCH clock rise time see Figure 19 -8 - 8 ns tCHCL clock fall time see Figure 19 -8 - 8 ns Shift register (UART mode 0) TXLXL serial port clock cycle time see Figure 18 16Tcy(clk) - 1333 - ns tQVXH output data set-up to clock rising edge time see Figure 18 13Tcy(clk) - 1083 - ns tXHQX output data hold after clock rising edge time see Figure 18 -Tcy(clk) + 20 - 103 ns tXHDX input data hold after clock rising edge time see Figure 18 -0 - 0 ns tXHDV input data valid to clock rising edge time see Figure 18 150 - 150 - ns SPI interface fSPI SPI operating frequency slave 0 CCLK ⁄ 6 0 2.0 MHz master - CCLK ⁄ 4 - 3.0 MHz |
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