PCA9543A_43B_43C_5

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 05 — 17 November 2008

5 of 23

NXP Semiconductors

PCA9543A/43B/43C

6.

Functional description

Refer to Figure 1 “Block diagram of PCA9543A/43B/43C”.

6.1 Device address

Following a START condition, the bus master must output the address of the slave it is

accessing. The address of the PCA9543A is shown in Figure 4. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW.

The last bit of the slave address defines the operation to be performed. When set to

logic 1 a read is selected, while a logic 0 selects a write operation.

The PCA9543B and PCA9543C are alternate address versions if needed for larger

systems or to resolve address conflicts. The data sheet will reference the PCA9543A, but

the PCA9543B and PCA9543C function identically except for the slave address.

6.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9543A, which will be stored in the control register. If multiple bytes are

received by the PCA9543A, it will save the last byte received. This register can be written

Fig 4.

Slave address PCA9543A

Fig 5.

Slave address PCA9543B

Fig 6.

Slave address PCA9543C

002aab169

1

1

1

0

0

A1

A0 R/W

fixed

hardware

selectable

002aab799

1

1

1

1

0

A1

A0 R/W

fixed

hardware

selectable

002aab800

0

1

1

0

0

A1

A0 R/W

fixed

hardware

selectable

Fig 7.

Control register

002aab181

X

X

INT

1

INT

0

X

X

B1

B0

channel selection bits

(read/write)

76543210

interrupt bits

(read only)

channel 0

channel 1

INT0

INT1