PCA9543A_43B_43C_5

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 05 — 17 November 2008

6 of 23

NXP Semiconductors

PCA9543A/43B/43C

6.2.1 Control register definition

One or several SCx/SDx downstream pair, or channel, is selected by the contents of the

control register. This register is written after the PCA9543A has been addressed. The

2 LSBs of the control byte are used to determine which channel is to be selected. When a

channel is selected, the channel will become active after a STOP condition has been

the channel is made active, so that no false conditions are generated at the time of

connection.

Remark: Channel 0 and channel 1 can be enabled at the same time. Care should be

taken not to exceed the maximum bus capacitance.

6.2.2 Interrupt handling

The PCA9543A provides 2 interrupt inputs, one for each channel, and one open-drain

interrupt output. When an interrupt is generated by any device, it will be detected by the

PCA9543A and the interrupt output will be driven LOW. The channel need not be active

for detection of the interrupt. A bit is also set in the control register.

Bit 4 and bit 5 of the control register corresponds to the INT0 and INT1 inputs of the

PCA9543A, respectively. Therefore, if an interrupt is generated by any device connected

to channel 1, the state of the interrupt inputs is loaded into the control register when a

read is accomplished. Likewise, an interrupt on any device connected to channel 0 would

cause bit 4 of the control register to be set on the read. The master can then address the

PCA9543A and read the contents of the control register to determine which channel

contains the device generating the interrupt. The master can then reconfigure the

PCA9543A to select this channel, and locate the device generating the interrupt and

clear it.

It should be noted that more than one device can provide an interrupt on a channel, so it is

up to the master to ensure that all devices on a channel are interrogated for an interrupt.

The interrupt inputs may be used as general purpose inputs if the interrupt function is not

required.

Table 4.

Control register: Write—channel selection; Read—channel status

D7

D6

INT1

INT0

D3

D2

B1

B0

Command

XXXXXXX

0

channel 0 disabled

1

channel 0 enabled

XXXXXX

0

X

channel 1 disabled

1

channel 1 enabled

00000000no channel selected;

power-up/reset default state

Table 5.

Control register: Read—interrupt

7

6

INT1

INT0

3

2

B1

B0

Command

XXX

0

XXXX

no interrupt on channel 0

1

interrupt on channel 0

XX

0

XXXXX

no interrupt on channel 1

1

interrupt on channel 1