AT91SAM7S161 datasheet(40/50 Pages) ATMEL

40 / 50 page

6175GS–ATARM–24-Dec-08

AT91SAM7S Series Summary

10.10 PWM Controller

• Four channels, one 16-bit counter per channel

• Common clock generator, providing thirteen different clocks

– One Modulo n counter providing eleven clocks

– Two independent linear dividers working on modulo n counter outputs

• Independent channel programming

– Independent enable/disable commands

– Independent clock selection

– Independent period and duty cycle, with double buffering

– Programmable selection of the output waveform polarity

– Programmable center or left aligned output waveform

10.11 USB Device Port (Does not pertain to AT91SAM7S32/16)

• USB V2.0 full-speed compliant, 12 Mbits per second.

• Embedded USB V2.0 full-speed transceiver

• Embedded 328-byte dual-port RAM for endpoints

• Four endpoints

– Endpoint 0: 8 bytes

– Endpoint 1 and 2: 64 bytes ping-pong

– Endpoint 3: 64 bytes

– Ping-pong Mode (two memory banks) for isochronous and bulk endpoints

• Suspend/resume logic

10.12 Analog-to-digital Converter

• 8-channel ADC

• 10-bit 384 Ksamples/sec. or 8-bit 583 Ksamples/sec. Successive Approximation Register

ADC

• ±2 LSB Integral Non Linearity, ±1 LSB Differential Non Linearity

• Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs

• External voltage reference for better accuracy on low voltage inputs

• Individual enable and disable of each channel

• Multiple trigger source

– Hardware or software trigger

– External trigger pin

– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger

• Sleep Mode and conversion sequencer

– Automatic wakeup on trigger and back to sleep mode after conversions of all

enabled channels

• Four of eight analog inputs shared with digital signals

AT91SAM7S161 Datasheet(PDF) 40 Page - ATMEL Corporation